Single event upsets (SEUs), or soft errors, are a problem in digital circuits located in environments that contain large numbers of particles that are likely to cause SEUs. An SEU occurs when particles, such as protons and heavy ions, passing through a digital circuit deposit enough charge to upset the logic state of the circuit. The susceptibility of high speed digital circuits to SEUs is due to the very fast nature of the SEU. The time scale for the deposition of the charge is typically about fifty picoseconds to three nanoseconds. This susceptibility is proportional to technology bandwidth indicating increased sensitivity with advances in technology. Standard silicon CMOS technology is becoming increasingly sensitive with reducing gate lengths.
Most very high speed logic is implemented in current steering logic (CSL). CSL implements Boolean functions by steering a current through differential transistor pairs to develop a differential output voltage across resistive devices, and incorporates current amplifiers, such as source or emitter followers, when increased drive capability is needed. CSL is the basis for silicon emitter-coupled logic (ECL) and current mode logic (CML), gallium arsenide (GaAS) source coupled FET logic (SCDL), some GaAs hetero-structure bipolar transistor (HBT) circuits, and can be found in other semiconductors and associated logic implementations.
Conventional SEU hardening approaches rely upon either system level triple modular redundancy coupled with voting logic circuitry or RF filtering to reduce bandwidth. A shortcoming of system level triple modular redundancy is the greater than 300% increase in complexity and power as well as increases in size and weight required in order to provide the hardening function. Furthermore, extensive redesign to existing systems is needed to incorporate the system level triple modular redundancy in order to implement SEU hardening. One shortcoming of RF filtering is the reduction of system speed.
One SEU hardening approach overcomes the shortcomings of the system level triple modular redundancy through functional redundancy at the transistor level by including three or more functionally equivalent circuit cell elements in parallel. SEU insensitive resistive devices are used in a summing element. If the cell is clocked, three or more clock distribution circuits are used for clock hardening. The function of the multiple circuit cell elements is such that an SEU is not sufficient to cause a logic error in the circuit output.
The parallel circuit cell element approach obtains a similar level of soft error hardening as the system level triple modular redundancy approach without the added complexity of voting logic circuitry and with less circuit area. Furthermore, it is implemented within an integrated circuit to allow "drop-in" replacement resulting in little system modification, and no integrated circuit fabrication process modifications. However, a problem exists with the parallel circuit cell element approach in that it has an undesirably high power consumption level, though less sensitive than triple modular redundancy.
Power consumption is an important factor in some applications, such as spacecraft systems, because increased power consumption results in the need to generate more power and the need to carry away more heat. Additional power consumption and heat dissipation elements result in a greater weight and complexity of the spacecraft which ultimately drives up system costs. Hence, prior art systems are typically designed to desirably minimize power consumption levels. Unfortunately, operating digital circuits at lower power consumption levels adversely affects the sensitivity of digital circuits to SEUs causing the digital circuit to suffer from unacceptably high numbers of SEUs.
Thus what is needed is an apparatus and method for dynamic SEU hardening of a digital circuit that does so efficiently and simply. Furthermore, what is needed is a method and apparatus that operates at the lowest power possible in a given environment and can be implemented within pre-existing circuitry, such as a spacecraft, with little system modification. In addition, what is needed is an apparatus that can be used in applications with varying SEU hardening needs in which an SEU adjustment variable is adjusted in response to the varying SEU hardening needs.